This invention relates generally to a semiconductor memory device suited for use in a display driver circuit for a matrix type display. In accordance with the prior art, there are two types of construction for a display driver. Namely, a display driver which has a random access memory (RAM) therein formed of ten elements, that is, transistors. As a result, circuit integration is low and it is difficult to construct a RAM of large capacity. In a second type of display driver, the display data is converted from serial to parallel in a peripheral portion of the circuit. The construction becomes complicated and it is impossible to access the refresh memory from the system side at free timing. Additionally, high speed data processing is necessary and it is difficult to reduce power consumption. Therefore, where portable equipment operating on batteries is concerned, it is difficult to enlarge the display capacity.
Presently, a line sequential scanning system is utilized for driving any flat type matrix displays, such as a liquid crystal display, plasma display, fluorescent display tube, electro-luminescent display, and the like. This is comparable to a dot sequential scanning system used with a cathode ray tube display. Therefore, in the signal side driving circuit for driving the above mentioned displays, display data of one-word unit, which is input from the system side comprising a central processing unit or a keyboard, is stored once in a refresh memory of the RAM type. It is necessary that the display data after being converted serial-parallel, be simultaneously supplied to many segment drivers in order drive the displays.
In the prior art, in order to convert serial-parallel, as stated above, it is necessary that the serial-parallel conversion circuit be comprised of both a shift register and a latch, provided outside of the refresh memory. Alternatively, the display data is converted serial-parallel at the same time of reading from the refresh memory by using a ten-transistor element RAMS cell (FIG. 1).
In a construction where the serial-parallel conversion is provided externally, the input/output circuit becomes complicated because the input/output circuit from the system side of the refresh memory, and the read circuit to the display side are in common. Additionally, at the time of reading to the display side, the input/output mode is restricted because access from the system side to the refresh memory is not possible.
On the other hand, when using a ten-element RAM cell, the number of elements and leads is large so that the area of the cell becomes large and it is impossible to form a large capacity RAM from the point of cost. Additionally, quickening the access time of the refresh memory is limited because the area of the cell is large.
What is needed is a semiconductor memory device of the RAM type which uses a reduced number of transistor elements and is readily integrated and accessed.